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ISL9200
Data Sheet October 4, 2005 FN9241.0
Charging System Safety Circuit
The ISL9200 is an integrated circuit (IC) optimized to provide a Li-ion battery redundant safety protection from failures of a charging system. The IC monitors the input voltage, the battery voltage, and the charge current. When any of the three parameters exceeds its limit, the IC turns off an internal P-channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-channel MOSFET when the die temperature exceeds 140C. Together with the battery charger IC and the protection module in a battery pack, the charging system using the ISL9200 has triple-level protection and is two-fault tolerant. The IC is designed to turn on the internal PFET slowly to avoid inrush current at power-up but will turn off the PFET quickly when input overvoltage is detected, in order to remove the power before any damage occurs. The ISL9200 has a logic warning output to indicate the fault and an enable input to allow the system to remove the input power.
Features
* Fully Integrated Protection Circuit for Three Protection Variables - User Programmable Overcurrent Protection Threshold - Input Overvoltage Protection in Less Than 1s - Battery Overvoltage Protection * High Immunity of False Triggering Under Transients * High Accuracy Protection Thresholds * Warning Output to Indicate the Occurrence of Faults * Enable Input * Thermal Enhanced DFN Package * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Cell Phones * Digital Still Cameras * PDAs and Smart Phones * Portable Instruments
Ordering Information
PART # ISL9200IRZ* (Note) PART TEMP. MARKING RANGE (C) 00Z -40 to 85 PACKAGE PKG. DWG. #
* Desktop Chargers
12 Ld 4x3 DFN L12.4x3 (Pb-free)
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Technical Brief TB379 "Thermal Characterization of Packaged Semiconductor Devices" * Technical Brief TB389 "PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages"
ISL9200EVAL1 ISL9200 Evaluation Board *Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL9200 (4x3 DFN) TOP VIEW
Typical Application Circuit
INPUT VIN VIN OUT ISL6292 BATTERY CHARGER VIN GND WRN ISL9200 ILIM VB EN RILIM GND WRN RVB BATTERY PACK + NC NC 1 2 3 4 5 6
12 NC 11 OUT EPAD 10 OUT 9 8 7 ILIM VB EN
C1
NOTE: EPAD must be electrically connected to the GND pin.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL9200
Absolute Maximum Ratings (Reference to GND)
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30V Output and VB Pin (OUT, VB) (Note 1) . . . . . . . . . . . . . . . -0.3 to 7V Other Pins (ILIM, WRN, EN) . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5V ESD Rating Human Body Model (Per JESD22-A114-B) . . . . . . . . . . . . .3000V Machine Model (Per EIA/JESD22 A115-A) . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance (Notes 2, 3) JA (C/W) JC (C/W) 4x3 DFN Package . . . . . . . . . . . . . . . . 41 3.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40C to 85C Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V to 6.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The maximum voltage rating for the VB pin under continuous operating conditions is 5.5V. All other pins are allowed to operate continuously at the absolute maximum ratings. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
PARAMETER POWER-ON RESET Rising VIN Threshold POR Hysteresis VIN Bias Current VIN Bias Current PROTECTIONS
Typical values are tested at VIN = 5V and 25C Ambient Temperature, maximum and minimum values are guaranteed over the recommended operating conditions, unless otherwise noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VPOR IVIN When enabled When disabled
2.4 0.75 30
2.58 100 0.9 60
2.7 1.05 100
V mV mA A
Input Overvoltage Protection (OVP) Input OVP Hysteresis Input OVP Falling Threshold Input OVP Propagation Delay Overcurrent Protection Overcurrent Protection Blanking Time Battery Overvoltage Protection Threshold Battery OVP Threshold Hysteresis Battery OVP Falling Threshold Battery OVP Blanking Time VB Pin Leakage Current Over Temperature Protection Rising Threshold Over Temperature Protection Falling Threshold LOGIC EN Input Logic HIGH EN Input Logic LOW EN Internal Pull Down Resistor WRN Output Logic Low WRN Output Logic High Leakage Current POWER MOSFET On Resistance
VOVP
6.65 6.55 -
6.8 60 1.0 170 4.4 75
7.0 100 1 1.07 4.475 20 -
V mV V s A s V mV V s nA C C
IOCP BTOCP VBOVP
VVB = 3V, RILIM = 25k
0.93 4.325
4.225 BTBOVP VVB = 4.4V -
180 140 90
1.5 100 Sink 5mA current -
200 0.35 -
0.4 400 0.8 1
V V k V A
RDS(ON)
Measured at 500mA, 4.3V < VIN < 6.5V
-
250
450
m
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ISL9200 Pin Descriptions
VIN (Pins 1, 2)
The input power source. The VIN can withstand 30V input.
VB (Pin 8)
Battery voltage monitoring input. This pin is connected to the battery pack positive terminal via an isolation resistor.
GND (Pin 3)
System ground reference.
ILIM (Pin 9)
Overcurrent protection threshold setting pin. Connect a resistor between this pin and GND to set the OCP threshold.
WRN (Pin 4)
WRN is an open-drain logic output that turns LOW when any protection event occurs.
OUT (Pins 10, 11)
Output pin.
NC (Pins 5, 6, 12)
No connection and must be left floating.
EPAD
The exposed pad at the bottom of the DFN package for enhancing thermal performance. Must be electrically connected to the GND pin.
EN (Pin 7)
Enable input. Pull this pin to low or leave it floating to enable the IC and force it to high to disable the IC.
Typical Applications
INPUT VIN OUT ISL6292 BATTERY CHARGER
C1
PART RILIM 25k
DESCRIPTION
ISL9200 ILIM VB EN RILIM GND WRN RVB BATTERY PACK +
RVB C1
200k to 1M 1F/16V X5R ceramic capacitor
Block Diagram
INPUT VIN Q1 Q2 OUT ISL6292 BATTERY CHARGER Q3
ILIM
POR PRE-REG REF R1
FET DRIVER
RILIM CP2 EA
0.8V CP1 R2 1.2V R3 Q4 Q5 R4 R5 EN BUF LOGIC CP3 VB R VB
+
WRN
GND
FIGURE 1. BLOCK DIAGRAM
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ISL9200 Typical Operating Performance
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted.
VIN (1V/div) OUT (1V/div)
VIN (2V/div)
OUT (2V/div)
Load Current (200mA/div) Time: 5ms/div
WRN (5V/div) Time: 2s/div
FIGURE 2. CAPTURED WAVEFORMS FOR POWER-UP. THE OUTPUT IS LOADED WITH A 10 RESISTOR
FIGURE 3. CAPTURED WAVEFORMS WHEN THE INPUT VOLTAGE STEPS FROM 6.5V TO 10.5V
Time: 200ms/div VIN (2V/div)
VIN (2V/div)
OUT (2V/div) OUT (2V/div)
WRN (5V/div)
WRN (5V/div)
Time: 5ms/div
FIGURE 4. CAPTURED WAVEFORMS WHEN THE INPUT GRADUALLY RISES TO THE INPUT OVERVOLTAGE THRESHOLD
FIGURE 5. TRANSIENT WHEN THE INPUT VOLTAGE STEPS FROM 7.5V TO 6.5V
VIN (2V/div)
Time: 20s/div
VIN (1V/div)
VB (1V/div)
OUT (2V/div) ILIM (1V/div) WRN (5V/div) Time: 500s/div
OUT (1V/div) WRN (5V/div)
FIGURE 6. TRANSIENT WAVEFORMS WHEN INPUT STEPS FROM ZERO TO 9V
FIGURE 7. BATTERY OVERVOLTAGE PROTECTION. THE IC IS LATCHED OFF AFTER 16 COUNTS OF PROTECTION. VB VOLTAGE VARIES BETWEEN 4.3V TO 4.5V
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ISL9200 Typical Operating Performance
Time: 200ms/div VIN (1V/div) OUT (1V/div) Load Current (500mA/div) WRN (5V/div)
Load Current (500mA/div) OUT (1V/div) WRN (5V/div)
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. (Continued)
Time: 10ms/div VIN (1V/div)
FIGURE 8. POWER-UP WAVEFORMS WHEN OUTPUT IS SHORT-CIRCUITED
FIGURE 9. ZOOMED-IN VIEW OF FIGURE 8 (BLUE: LOAD CURRENT; PINK: OUT PIN VOLTAGE)
1200 1000 800 ENABLED 600 400 200 0
1000 900 800 CURRENT (A) 700 600 500 400 300 200 100 0 5 10 15 20 25 30 35 0 -50
6.5V/ENABLED 4.3V/ENABLED 5V/ENABLED 30V/ENABLED
INPUT BIAS CURRENT (A)
DISABLED
30V/DISABLED 6.5V/DISABLED 5V/DISABLED 4.3V/DISABLED
-20
10
40
70
100
130
INPUT VOLTAGE (V)
TEMPERATURE (C)
FIGURE 10. INPUT BIAS CURRENT vs INPUT VOLTAGE WHEN ENABLED AND DISABLED
FIGURE 11. INPUT BIAS CURRENT AT DIFFERENT INPUT VOLTAGES WHEN ENABLED AND DISABLED
2.6 2.58 RISING THRESHOLD 2.56
6.95 6.9 RISING THRESHOLD 6.85 VOVP (V) FALLING THRESHOLD
VPOR (V)
2.54 2.52 2.5 2.48 2.46 -50
6.8 6.75 6.7 6.65 -50 FALLING THRESHOLD
-20
10
40
70
100
130
-20
10
40
70
100
130
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 12. VPOR vs TEMPERATURE
FIGURE 13. INPUT OVERVOLTAGE PROTECTION THRESHOLDS vs TEMPERATURE
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ISL9200 Typical Operating Performance
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. (Continued)
200 CURRENT LIMIT = 1A 195 190 185 BTOCP (s) 180 175 170 165 3V 160 155 10 40 70 100 130 150 -50 -20 10 40 70 100 130
1050 1040 1030 1020 IOCP (mA) 1010 1000 990 980 970 960 -50 -20 4.3V 5V 6.5V
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 14. OVERCURRENT PROTECTION THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES
FIGURE 15. OVERCURRENT PROTECTION BLANKING TIME vs TEMPERATURE
515 510 505 500 IOCP (mA) 495 490 485 480 475 470 -50 -20 10 5V 40 70 100 130 3V VBOVP (V) 6.5V 4.3V
4.42 4.41 4.4 4.39 4.38 4.37 4.36 4.35 4.34 4.33 4.32 -50 -20 10 40 70 100 130 FALLING THRESHOLDS FOR 4.5V, 5V AND 6.5V INPUT RISING THRESHOLDS FOR 4.5V, 5V AND 6.5V INPUT
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 16. OVERCURRENT PROTECTION THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES
FIGURE 17. BATTERY VOLTAGE OVP THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES
200 VB PIN LEAKAGE CURRENT (nA) 195 190 185 BTBOVP (s) 180 175 170 165 160 155 150 -50 -20 10 40 70 100 130
3.0 TESTED AT 5V 2.5 2.0 1.5 1.0 0.5 0 -50
-20
10
40
70
100
130
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 18. BATTERY OVP BLANKING TIME
FIGURE 19. VB PIN LEAKAGE CURRENT vs TEMPERATURE
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ISL9200 Typical Operating Performance
2.0 EN PIN INTERNAL PULL-DOWN (k) -20 10 40 70 100 130 1.8 1.6 EN THRESHOLD (V) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. (Continued)
250 240 230 220 210 200 190 180 170 160 150 -50 -20 10 40 70 100 130
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 20. EN INPUT THRESHOLD vs TEMPERATURE
FIGURE 21. EN PIN INTERNAL PULL-DOWN RESISTANCE
0.5 3V 0.4 4.3V
RDS(ON) ()
0.3
0.2
5V 6.5V
0.1
0 -50
-20
10
40
70
100
130
TEMPERATURE (C)
FIGURE 22. ON RESISTANCE vs TEMPERATURE AT DIFFERENT INPUT VOLTAGES
Theory of Operation
The ISL9200 is an integrated circuit (IC) optimized to provide a redundant safety protection to a Li-ion battery from charging system failures. The IC monitors the input voltage, the battery voltage, and the charge current. When any of the above three parameters exceeds its limit, the IC turns off an internal P-channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-channel MOSFET when the temperature exceeds 140C. Together with the battery charger IC and the protection module in a battery pack, the charging system has triple-level protection from overcharging the Li-ion battery and is two-fault tolerant. The ISL9200 protects up to 30V input voltage.
Power-Up
The ISL9200 has a power-on reset (POR) threshold of 2.6V with a built-in hysteresis of 100mV. Before the input voltage reaches the POR threshold, the internal power PFET is off. Approximately 10ms after the input voltage exceeds the POR threshold, the IC resets itself and begins the soft-start. The 10ms delay allows any transients at the input during a hot insertion of the power supply to settle down before the IC starts to operate. The soft-start slowly turns on the power PFET to reduce the inrush current as well as the input voltage drop during the transition. The power-up behavior is illustrated in Figure 2.
Input Overvoltage Protection (OVP)
The input voltage is monitored by the comparator CP1 in the Block Diagram (Figure 1). CP1 has an accurate reference of 1.2V from the bandgap reference. The OVP threshold is set by the resistive divider consisting of R1 and R2. The
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ISL9200
protection threshold is set to 6.8V. When the input voltage exceeds the threshold, the CP1 outputs a logic signal to turn off the power PFET within 1s (see Figure 3) to prevent the high input voltage from damaging the electronics in the handheld system. The hysteresis for the input OVP threshold is given in the Electrical Specification. When the input overvoltage condition is removed, the ISL9200 reenables the output by running through the soft-start, as shown in Figure 5. Because of the 10ms second delay before the soft-start, the output is never enabled if the input rises above the OVP threshold quickly, as shown in Figure 6. event. When the total count reaches 16, the power PFET is turned off permanently unless the input power is recycled or the enable pin is toggled. Figure 8 and Figure 9 illustrate the waveforms during the power-up when the output is shortcircuited to ground.
Internal Over Temperature Protection
The ISL9200 monitors its own internal temperature to prevent thermal failures. When the internal temperature reaches 140C, the IC turns off the P-channel power MOSFET. The IC does not resume operation until the internal temperature drops below 90C.
Battery Overvoltage Protection
The battery voltage OVP is realized with the VB pin. The comparator CP3, as shown in Figure 1, monitors the VB pin and issues an overvoltage signal when the battery voltage exceeds the 4.4V battery OVP threshold. The threshold has 75mV built-in hysteresis. The comparator CP3 has a built-in 180s blanking time to prevent any transient voltage from triggering the OVP. If the OVP situation still exists after the blanking time, the power PFET is turned off. The control logic contains a 4-bit binary counter that if the battery overvoltage event occurs 16 times, the power PFET is turned off permanently, as shown in Figure 7. Recycling the input power or toggling the enable (EN) input will reset the counter and restart the ISL9200. The resistor between the VB pin and the battery, RVB, as shown in the Typical Applications circuit, is an important component. This resistor provides a current limit in case the VB pin is shorted to the input voltage under a failure mode. The VB pin leakage current under normal operation is negligible to allow a resistance of 200k to 1M be used.
External Enable Control
The ISL9200 offers an enable (EN) input. When the EN pin is pulled to logic HIGH, the protection IC is shut down. The internal control circuit as well as the power PFET are turned off. Both 4-bit binary counters for the battery OVP and the OCP are reset to zero when the IC is re-enabled. The EN pin has an internal 200k pull-down resistor. Leaving the EN pin floating or driving it to below 0.4V enables the IC.
Warning Indication Output
The WRN pin is an open-drain output that indicates a LOW signal when any of the three protection events happens. This allows the microprocessor to give an indication to the user to further enhance the safety of the charging system.
Applications Information
The ISL9200 is designed to meet the "Lithium-Safe" criteria when operating together with the ISL6292 family Li-ion battery chargers. The "Lithium-Safe" criteria requires the charger output to fall within the green region shown in Figure 23 under normal operating conditions and NOT to fall in the red region when there is a single fault in the charging system. Taking into account the safety circuit in a Li-ion battery pack, the charging system is allowed to have two faults without creating hazardous conditions for the battery cell. The output of any ISL6292 family chargers, such as the ISL6292C, has a typical I-V curve shown with the blue lines under normal operation, which is within the green region. The function of the ISL9200 is to add an redundant protection layer such that, under any single fault condition, the charging system output does not exceed the I-V limits shown with the red lines. As a result, the charging system adopting the ISL9200 and the ISL6292C chip set can easily pass the "Lithium-Safe" criteria test procedures. The ISL9200 is a simple device that requires only three external components, in addition to the ISL6292 charger circuit, to meet the "Lithium-Safe" criteria, as shown in the Typical Application Circuit. The selection of the current limit resistor RILIM is given in the Overcurrent Protection section.
Overcurrent Protection (OCP)
The current in the power PFET is limited to prevent charging the battery with an excessive current. The current is sensed using the voltage drop across the power FET after the FET is turned on. The reference of the OCP is generated using a sensing FET Q2, as shown in Figure 1. The current in the sensing FET is forced to the value programmed by the ILIM pin. The size of the power FET Q1 is 31,250 times the size of the sensing FET. Therefore, when the current in the power FET is 31,250 times the current in the sensing FET, the drain voltage of the power FET falls below that of the sensing FET. The comparator CP2 then outputs a signal to turn off the power FET. The OCP threshold can be calculated using the following equation:
0.8V 25000 I LIM = --------------- 31250 = --------------R ILIM R ILIM
where the 0.8V is the regulated voltage at the ILIM pin. The OCP comparator CP2 has a built-in 170s delay to prevent false triggering by transient signals. The OCP function also has a 4-bit binary counter that accumulates during an OCP 8
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ISL9200
RVB Selection
The RVB prevents a large current from the VB pin to the battery terminal, in case the ISL9200 fails. The recommended value should be between 200k to 1M. With 200k resistance, the worst case current flowing from the VB pin to the charger output is,
(30V - 4.2V)/200k = 130A,
ISL9200 MCU
VIO RPU Q4 WRN RWRN
assuming the VB pin voltage is 30V under a failure mode and the battery voltage is 4.2V. Such a small current can be easily absorbed by the bias current of other components in the handheld system. Increasing the RVB value reduces the worst case current, but at the same time increases the error for the 4.4V battery OVP threshold. The error of the battery OVP threshold is the original accuracy at the VB pin given in the Electrical Specification plus the voltage built across the RVB by the VB pin leakage current. The VB pin leakage current is less than 20nA, as given in the Electrical Specification. With the 200k resistor, the worst-case additional error is 4mV and with a 1M resistor, the worst-case additional error is 20mV.
1000 ISL9200 LIMITS ISL6292C LIMITS
Q5 R5
EN REN
FIGURE 24. DIGITAL SIGNAL INTERFACE BETWEEN ISL9200 AND MCU
Capacitor Selection
The input capacitor (C1 in the Typical Application Circuit) is for decoupling. Higher value reduces the voltage drop or the over shoot during transients. Two scenarios can cause the input voltage over shoot. The first one is when the AC adapter is inserted live (hot insertion) and the second one is when the current in the power PFET of the ISL9200 has a step-down change. Figure 25 shows an equivalent circuit for the ISL9200 input. The cable between the AC/DC converter output and the handheld system input has a parasitic inductor. The parasitic resistor is the lumped sum of various components, such as the cable, the adapter output capacitor ESR, the connector contact resistance, and so on.
CHARGE CURRENT (mA)
0
1
2
3
4
5
6
C1
L
R
C2
BATTERY VOLTAGE (V)
FIGURE 23. LITHIUM-SAFE OPERATING REGIONS
AC/DC
ISL9200
Interfacing to MCU
The ISL9200 has the enable (EN) and the warning (WRN) digital signals that can be interfaced to a microcontroller unit (MCU). Both signals can be left floating if not used. When interfacing to an MCU, it is highly recommended to insert a resistor between the ISL9200 signal pin and the MCU GPIO pin, as shown in Figure 24. The resistor creates an isolation to limit the current, in case a high voltage shows up at the ISL9200 pins under a failure mode. The recommended resistance ranges from 10k to 100k. The selection of the REN is dependent on the IO voltage (VIO) of the MCU. REN should be selected so that the ISL9200 EN pin voltage is above the disable threshold when the GPIO output of the MCU is high.
ADAPTER
CABLE
HANDHELD SYSTEM
FIGURE 25. EQUIVALENT CIRCUIT FOR THE ISL9200 INPUT
During the load current step-down transient, the energy stored in the parasitic inductor is used to charge the input decoupling capacitor C2. The ISL9200 is designed to turn off the power PFET slowly during the OCP, the battery OVP event, and when the device is disabled via the EN pin. Because of such design, the input over shoot during those events is not significant. During an input OVP, however, the PFET is turned in less than 1s and can lead to significant over shoot. Higher capacitance reduces this type of over shoot.
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ISL9200
The over shoot caused by a hot insertion is not very dependent on the decoupling capacitance value. Especially when ceramic type capacitors are used for decoupling. In theory, the over shoot can rise up to twice of the DC output voltage of the AC adapter. The actual peak voltage is dependent on the damping factor that is mainly determined by the parasitic resistance (R in Figure 25). In practice, the input decoupling capacitor is recommended to use a 16V X5R dielectric ceramic capacitor with a value between 0.1F to 1F. The output of the ISL9200 and the input of the charging circuit typically share one decoupling capacitor. The selection of that capacitor is mainly determined by the requirement of the charging circuit. When using the ISL6292 family chargers, a 1F, 6.3V, X5R capacitor is recommended.
Layout Recommendation
The ISL9200 uses a thermally enhanced DFN package. The exposed pad under the package should be connected to the ground plane electrically as well as thermally. A grid of 1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5 vias per row is recommended (refer to the ISL9200EVAL1 evaluation board layout). The vias should be about 0.3mm to 0.33mm in diameter. Use some copper on the component layer if possible to further improve the thermal performance but it is not mandatory. Since the ISL9200 is a protection device, the layout should also pay attention to the spacing between tracks. When the distance between the edges of two tracks is less than 0.76mm, an FMEA (failure mechanism and effect analysis) should be performed to ensure that a short between those two tracks does not lead to the charger output exceeding the "Lithium-Safe" region limits. Intersil will have the FMEA document for the solution using the ISL9200 and the ISL6292C chip set but the layout FMEA should be added as part of the analysis.
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FN9241.0 October 4, 2005
ISL9200 Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-VGED-4 ISSUE C) MILLIMETERS SYMBOL A
E
MIN 0.80 0.18 3.15 1.55 0.20 0.30
NOMINAL 0.90 0.20 REF 0.23 4.00 BSC 3.30 3.00 BSC 1.70 0.50 BSC 0.40 12 6
MAX 1.00 0.05 0.30 3.40 1.80 0.50
NOTES 5,8 7,8 7,8 8 2 3 Rev. 1 2/05
A1 A3 b D
6 INDEX AREA TOP VIEW B
D2 E
// 0.10 0.08 C C
E2 e k L N Nd
A SIDE VIEW C SEATING PLANE D2 (DATUM B) 6 INDEX AREA (DATUM A) E2 E2/2 NX L N 8 N-1 e (Nd-1)Xe REF. BOTTOM VIEW (A1) 5 0.10 NX b 1 2 NX k D2/2 A3
7
8
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
M C AB C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
NX (b) 5
L e
SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN9241.0 October 4, 2005

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